Sr Staff AMS Verification Engineer

Job Description

We are seeking creative and hardworking engineers to join our outstanding Analog/ Mixed- Signal Verification team.

You will collaborate with systems and design teams to facilitate top down design methodology. You will also work with chip and DV leads to plan, setup, & execute AMS/UVM verification. This position will play a vital role streamlining development methodology for our organization.

Key responsibilities:

CAD


• Project setup: tools, versions and technology


• Set up and manage project environments and workspaces


• Maintaining PDK integrity and flawless integration in project databases


• Defining and owning tape-out flows and tape-out quality insurance


• Build database structure with revision control system


• Develop scripts and automation tools to optimise design flows


• Automatize verification with python script command line and pyqt gui


• Automatize cadenceIC work with skill code script and gui


• Setup virtuoso environment for mixed-signal verification


• First CAD contact support for the team

AMS Verification


• Validate system feasibility and integrity with verilogams or system Verilog model Top-down Design


• Automatize top level block connection with EDA skill and python scripts


• Develop behavioral analog model (verilogams/system Verilog)


• Promote good practice and support analog designer with model writing


• Do analog focused Mixed- Signal Verification


• Create and maintain verification plans + tracking. Measurement and analysis of regression results


• Analog/ Mixed- Signal self-checking simulation


• Team up and collaborate with colleagues from analog and digital design and verification, as well as concept engineering


• Collaborate with multi-functional teams to streamline chip-level integration


• You will contribute to a team that performs verification planning and AMS simulation on full custom ASI Cs


• Develop test plans, test benches, and verification methodologies to verify the microarchitecture and design


• Performing regression debug support and other flow/infrastructure development


• Independent Interpretation of analog circuit schematics into abstract models

Qualifications


• MS or higher in Electrical Engineering


• 5+ years in CAD support or design flow development in a microelectronics setting


• Strong knowledge of Cadence tools and IC design methodologies


• Proficient in scripting (TCL, shell, Python, etc. )


• Experience with data management tools such as Git or Cliosoft


• Solid understanding of the full IC design process


• 8+ years of analog design knowhow and analog mixed-signal verification know-how


• Strong background in analog integrated circuit design


• Strong background in System Verilog for real number modeling (RNM) modeling, test bench development & verification


• Solid understanding and hands on experience on the design of mixed signal designs


• Possess outstanding analytical and problem-solving skills


• Teaming closely with digital/analog designers, applications engineers, and manufacturing tests to support both pre-silicon verification and post-silicon validation efforts


• Ability to create, evaluate, debug, and improve a verification process